Field of the Invention
The present invention relates to a programming method for a NAND flash memory, and in particular to a flash memory with less degradation in reliability even though the flash memory repeatedly performs writing and erasing operations.
Description of the Related Art
An equivalent circuit of a cell array of a NAND-type flash memory is shown in FIG. 1. In a P-well, a plurality of transistors constituting NAND string(s) are formed. A NAND string includes a plurality of memory cells connected in series, a source line selection transistor connected to an end of the memory cells, and a bit line selection transistor connected to the other end of the memory cells. In the P-well, a plurality of the NAND strings are formed in the column direction. The NAND strings in one P-well constitute a block.
A source line SL is coupled to a diffusion region (a source region) of the source line selection transistor, and a bit line BL is coupled to a diffusion region (a drain region) of the bit line selection transistor. A plurality of word lines WL1, WL2, . . . , WLn are formed in the row direction which crosses with the NAND string. Each word line WL is connected to the control gates of the memory cells in the corresponding row. A selection gate line SGS is connected to the selection gates of the source line selection transistors in the corresponding row. A selection gate line DSG is connected to the selection gates of the bit line selection transistors in the corresponding row. When the source line selection transistor is conducted by the selection gate line SGS, the NAND string is coupled to the source line SL. When the bit line selection transistor is conducted by the selection gate line DSG, the NAND string is coupled to the bit line BL.
The NAND-type flash memory erases data in blocks. In the erase operation, 0V or voltage lower than the P-well is applied to the word lines of the selected block, and an erase pulse of positive voltage is applied to the P-well. In the programming (write-in) operation, 0V is applied to the P-well and high voltage is applied to the selected word line. 0V or positive potential is applied to the bit line BL, but in the case of 0V, the silicon surface of the selected cell becomes 0V, tunnel currents of electrons flow from the silicon substrate to the floating gate, and the threshold value of the memory cell becomes higher than a specified value (please refer to Japan Patent Publication No. 2014-049149).
In the conventional NAND-type flash memory, if the write-in operation and erase operation are performed repeatedly, degradation of the film quality of the oxide film under the floating gate occurs, and defection, such as the write-in defection or data variation following a period of time after the data is written, is generated. In such cases, there are issues where the number of rewriting data is limited, and the reliability cannot be assured if the number exceeds the threshold value. There are several reasons that the oxide film degrades, and one is that the oxide film degrades during the transition from the application of the erase pulse to the P-well to the write-in operation. After the erase pulse is applied to the P-well, the interval until the writing pulse applied to the word line is varied to perform the data rewriting, and the I-V characteristics of the cell are measured. The results of this measurement are shown in FIG. 2. Specifically, the initial I-V characteristic and the I-V characteristics which are measured after rewriting the data up to ten thousand times with three kinds of intervals: 0.05 second (solid line), 0.5 (dash line), and 5 second (dot line) are shown. From the diagram, it can be understood that the I-V characteristic changes more relative to the initial I-V characteristic as the interval becomes longer. Namely, if the interval between the erase operation and the write-in operation becomes longer, the trap level of the silicon interface increases, and thus the dependency between the I-V characteristic and the potential of the control gate decreases. Therefore, it is considered that the period from the application of the erase pulse to the write-in operation causes the oxide film to degrade. This degradation of the oxide film will reduce the reliability of the micronized memory cell and decrease the maximum number of data-rewrites of which the reliability can be assured.
The purpose of the invention is to provide a programming method for a NAND-type flash memory that solves the above problems and reduces the degradation of the reliability caused by rewriting data.